vishay siliconix SUD20N10-66L document number: 62815 s13-0629-rev. a, 25-mar-13 www.vishay.com 1 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: pmostechsupport@vishay.com n-channel 100 v (d-s) mosfet features ? trenchfet ? power mosfet ?100 % r g and uis tested ? material categorization: for definitions of compliance please see www.vishay.com/doc?99912 applications ? dc/dc converters ? dc/ac inverters ? motor drives notes: a. duty cycle ? 1 %. b. see soa curve for voltage derating. c. when mounted on 1" square pcb (fr-4 material). d. base on t c = 25 c. product summary v ds (v) r ds(on) ( ? ) max. i d (a) q g (typ.) 100 0.066 at v gs = 10 v 18.2 19.8 0.080 at v gs = 4.5 v 13.2 to-252 s g d top view drain connected to tab ordering information: SUD20N10-66L-ge3 (lead (pb)-free and halogen-free) n-channel mosfet g d s absolute maximum ratings (t c = 25 c, unless otherwise noted) parameter symbol limit unit drain-source voltage v ds 100 v gate-source voltage v gs 20 continuous drain current t c = 25 c i d 16.9 a t c = 70 c 13.6 pulsed drain current (t = 300 s) i dm 25 avalanche current i as 15 single avalanche energy a l = 0.1 mh e as 11.25 mj maximum power dissipation a t c = 25 c p d 41.7 b w t a = 25 c c 2.1 operating junction and storage temperature range t j , t stg - 55 to 150 c thermal resistance ratings parameter symbol limit unit junction-to-ambient (pcb mount) c r thja 60 c/w junction-to-case (drain) r thjc 3
vishay siliconix SUD20N10-66L document number: 62815 s13-0629-rev. a, 25-mar-13 www.vishay.com 2 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: pmostechsupport@vishay.com notes: a. pulse test; pulse width ? 300 s, duty cycle ? 2 %. b. guaranteed by design, not subject to production testing. c. independent of operating temperature. stresses beyond those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condit ions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. specifications (t j = 25 c, unless otherwise noted) parameter symbol test conditions min. typ. max. unit static drain-source breakdown voltage v ds v gs = 0 v, i d = 250 a 100 v gate threshold voltage v gs(th) v ds = v gs , i d = 250 a 1.2 3 gate-body leakage i gss v ds = 0 v, v gs = 20 v 250 na zero gate voltage drain current i dss v ds = 100 v, v gs = 0 v 1 a v ds = 100 v, v gs = 0 v, t j = 125 c 50 v ds = 100 v, v gs = 0 v, t j = 150 c 250 on-state drain current a i d(on) v ds ?? 10 v, v gs = 10 v 20 a drain-source on-state resistance a r ds(on) v gs = 10 v, i d = 6.6 a 0.055 0.066 ? v gs = 4.5 v, i d = 6 a 0.066 0.080 forward transconductance a g fs v ds = 15 v, i d = 6.6 a 25 s dynamic b input capacitance c iss v ds = 50 v, v gs = 0 v, f = 1 mhz 860 pf output capacitance c oss 85 reverse transfer capacitance c rss 40 total gate charge c q g v ds = 50 v, v gs = 10 v, i d = 6.6 a 19.8 30 nc gate-source charge c q gs 3.6 gate-drain charge c q gd 4.1 gate resistance r g f = 1 mhz 0.4 2 4 ? tu r n - o n d e l ay t i m e c t d(on) v dd = 50 v, r l = 9.6 ? i d ? 5.2 a, v gen = 10 v, r g = 1 ? 816 ns rise time c t r 11 20 turn-off delay time c t d(off) 18 27 fall time c t f 510 tu r n - o n d e l ay t i m e c t d(on) v dd = 50 v, r l = 9.6 ? i d ? 5.2 a, v gen = 4.5 v, r g = 1 ? 38 57 rise time c t r 58 87 turn-off delay time c t d(off) 18 27 fall time c t f 816 drain-source body diode ratings and characteristics b t c = 25 c continuous current i s 16.9 a pulsed current i sm 25 forward voltage a v sd i f = 5.2 a, v gs = 0 v 0.8 1.5 v reverse recovery time t rr i f = 5.2 a, di/dt = 100 a/s 34 51 ns peak reverse recovery current i rm(rec) 35a reverse recovery charge q rr 50 75 nc
vishay siliconix SUD20N10-66L document number: 62815 s13-0629-rev. a, 25-mar-13 www.vishay.com 3 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: pmostechsupport@vishay.com typical characteristics (25 c, unless otherwise noted) output characteristics transfer characteristics transconductance 0 5 10 15 20 25 0 0.5 1 1.5 2 i d - drain current (a) v ds - drain-to-source voltage (v) v gs = 10 v thru 7 v v gs = 3 v v gs = 4 v 0 1 2 3 4 5 0 1 2 3 4 i d - drain current (a) v gs - gate-to-source voltage (v) t c = 25 c t c = 125 c t c = - 55 c 0 10 20 30 40 0 3 6 9 12 g fs - transconductance (s) i d - drain current (a) t c = 25 c t c = 125 c t c = - 55 c on-resistance s. drain current on-resistance s. gate-to-source voltage gate charge 0.04 0.05 0.06 0.07 0.08 0.09 0 5 10 15 20 25 r ds(on) - on-resistance () i d - drain current (a) v gs =4.5v v gs = 10 v 0.03 0.06 0.09 0.12 0.15 2 4 6 8 10 r ds(on) - on-resistance () v gs - gate-to-source voltage (v) t j = 125 c t j = 25 c i d = 6.6 a 0 2 4 6 8 10 0 6 12 18 24 v gs - gate-to-source voltage (v) q g - total gate charge (nc) v ds = 80 v v ds = 25 v v ds = 50 v i d = 6.6 a
vishay siliconix SUD20N10-66L document number: 62815 s13-0629-rev. a, 25-mar-13 www.vishay.com 4 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: pmostechsupport@vishay.com typical characteristics (25 c, unless otherwise noted) source-drain diode forward voltage capacitance on-resistance vs. junction temperature 0.1 1 10 100 0.0 0.2 0.4 0.6 0.8 1.0 1.2 i s - source current (a) v sd - source-to-drain voltage (v) t j = 150 c t j = 25 c 0 250 500 750 1000 1250 0 20 40 60 80 100 c - capacitance (pf) v ds - drain-to-source voltage (v) c iss c oss c rss 0.45 0.9 1.35 1.8 2.25 - 50 - 25 0 25 50 75 100 125 150 r ds(on) - on-resistance (normalized) t j - junction temperature ( c) v gs = 4.5 v, i d = 6 a v gs = 10 v, i d = 6.6 a threshold voltage drain source breakdown vs. junction temperature current derating 1.2 1.5 1.8 2.1 2.4 2.7 - 50 - 25 0 25 50 75 100 125 150 v gs(th) (v) t j - temperature ( c) i d = 250 a 102 107 112 117 122 127 - 50 - 25 0 25 50 75 100 125 150 v ds (v) drain-to-source voltage t j - temperature ( c) i d = 250 a 0 5 10 15 20 0 25 50 75 100 125 150 i d - drain current (a) t c - case temperature ( c)
vishay siliconix SUD20N10-66L document number: 62815 s13-0629-rev. a, 25-mar-13 www.vishay.com 5 this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 for technical questions, contact: pmostechsupport@vishay.com typical characteristics (25 c, unless otherwise noted) vishay siliconix maintains worldwide manufacturing capability. pr oducts may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?62815 . single pulse avalanche current capability vs. time 1 10 0.0001 0.00001 0.000001 0.001 0.01 i dav (a) time (s) t j = 25 c t j = 150 c safe operating area 0.01 0.1 1 10 100 0.1 1 10 100 i d - drain current (a) v ds - drain-to-source voltage (v) * v gs > minimum v gs at which r ds(on) is specified dc, 10 s 1 s, 100 ms limited by r ds(on) * 1 ms t c = 25 c single pulse bvdss limited 10 ms 100 s normalized thermal transient impedance, junction-to-case square wave pulse duration (s) 2 1 0.1 0.01 10 -4 10 -3 10 -2 110 10 -1 normalized effective transient thermal impedance 0.2 0.1 duty cycle = 0.5 30 0.02 0.05 single pulse
package information www.vishay.com vishay siliconix revision: 16-may-16 1 document number: 71197 for technical questions, contact: pmostechsupport @vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 to-252aa case outline notes ? dimension l3 is for reference only. l3 d l4 l5 b b2 e1 e1 d1 c a1 gage plane height (0.5 mm) e b3 e c2 a l h millimeters inches dim. min. max. min. max. a 2.18 2.38 0.086 0.094 a1 - 0.127 - 0.005 b 0.64 0.88 0.025 0.035 b2 0.76 1.14 0.030 0.045 b3 4.95 5.46 0.195 0.215 c 0.46 0.61 0.018 0.024 c2 0.46 0.89 0.018 0.035 d 5.97 6.22 0.235 0.245 d1 4.10 - 0.161 - e 6.35 6.73 0.250 0.265 e1 4.32 - 0.170 - h 9.40 10.41 0.370 0.410 e 2.28 bsc 0.090 bsc e1 4.56 bsc 0.180 bsc l 1.40 1.78 0.055 0.070 l3 0.89 1.27 0.035 0.050 l4 - 1.02 - 0.040 l5 1.01 1.52 0.040 0.060 ecn: t16-0236-rev. p, 16-may-16 ? dwg: 5347
application note 826 vishay siliconix document number: 72594 www.vishay.com revision: 21-jan-08 3 application note recommended minimum pads for dpak (to-252) 0.420 (10.668) recommended mi nimum pads dimensions in inches/(mm) 0.224 (5.690) 0.180 (4.572) 0.055 (1.397) 0.243 (6.180) 0.087 (2.202) 0.090 (2.286) return to index return to index
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